-- Sumador resultado de 0 a 127

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity sumar is
port(a,b: in std_logic_vector(7 downto 0);
     output: out std_logic_vector(7 downto 0));
end sumar;

architecture behavior of sumar is
--signal s: std_logic_vector(7 downto 0);
--signal c: std_logic;
--signal xor1: std_logic_vector(7 downto 0);
--signal and1: std_logic_vector(7 downto 0);
--signal and_xor: std_logic_vector(7 downto 0);

--xor1 = X XOR Y
--and1 = X AND Y
--and_xor = Z AND (X XOR Y)
-- S = X XOR Y XOR Z
-- C = (X AND Y) OR (Z AND (X XOR Y))
begin
sum: process(a,b)
begin
--for i in 0 to 7 loop
	--xor1(i) <= a(i) XOR b(i);
	--and1(i) <= a(i) AND b(i);
	--and_xor(i) <= c AND xor1(i);
	--s(i) <= xor1(i) XOR carry;
	--c <= and1(i) OR and_xor(i);
	--sumita := s(i) OR c;
	--output(i) <= sumita;
output <= a + b;

end process sum;
end behavior; 


